A metal-oxide-semiconductor (MOS) transistor is a semiconductor device that has heavily-doped source and drain regions which are separated by a lightly-doped channel region of the opposite conductive type. A conductive gate is formed above the channel region and insulated from the channel region by a gate oxide layer. The conductive gate of a MOS transistor is typically formed with doped polysilicon.
In some high voltage applications, such as DC-DC converters or switching regulators, high voltage integrated circuit devices or power transistors are used. A double-diffused MOS (DMOS) transistor is a power transistor commonly used in high-voltage applications (20 to 500 volts) because of their high breakdown voltage characteristics and compatibility with CMOS fabrication technology. A DMOS transistor has a lightly-doped drain region, also referred to as a drift region, that lies between the channel region and the heavily-doped drain region. The lightly-doped drift region carries the current flow between the source and drain and can sustain a voltage drop greater than that of traditional CMOS transistors.
DMOS transistors can be formed as vertical devices or lateral devices. A vertical DMOS transistor has source and drain regions that are vertically spaced apart and at least a portion of the current path between the source and drain is vertical or perpendicular to the planar surface of the semiconductor layer. The vertical DMOS transistor is typically formed using a heavily doped semiconductor substrate as the drain region. A lateral DMOS (or LDMOS transistor) has source and drain regions that are horizontally spaced apart and a current path between the source and drain is horizontal only or parallel to the planar surface of the semiconductor layer.
A vertical DMOS transistor can be formed using a planar gate or a trench gate. In a trench DMOS transistor, the gate electrode is formed in a trench and the channel is formed in a vertical region along the sidewall of the trench. The trench DMOS transistor has a vertical current path with the source region on the top side and the drain terminal on the back side of the transistor device. Trench DMOS transistors are typically more expensive to manufacture and have higher gate capacitance as the entire gate is formed in a trench and surrounded by the semiconductor substrate.
FIG. 1 is a cross-sectional view of a conventional planar vertical DMOS transistor. In the present example, an N-type planar vertical DMOS transistor is shown. Referring to FIG. 1, a planar vertical DMOS transistor 100 is formed on an N++ substrate 102 as the drain region and an N-type semiconductor layer 104 as the drain drift region. The N-type semiconductor layer 104 is typically an N-type epitaxial layer. A planar gate 110, typically a polysilicon gate, is formed on a top surface of the semiconductor layer 104 and is insulated from the semiconductor layer by a thin gate oxide layer 108. N+ source regions 112 are formed in the semiconductor layer 104 on either sides of the planar gate 110. The N+ source regions 112 are formed inside P+ body regions 114. The channel region of the planar vertical DMOS transistor 100 is formed in a lateral region where the body region 114 overlaps the planar gate 110. The current path between the drain region (N++ substrate 102) and the source region 112 includes a vertical current path in the drain drift region (N-type semiconductor layer 104) and a lateral current path through the channel region.
In the planar vertical DMOS transistor 100 of FIG. 1, the overlap of the planar gate to the N-type semiconductor layer 104 outside of the channel region results in a gate-to-bulk or gate-to-drain overlap capacitance Cgd. This parasitic capacitance Cgd is a primary contributor to efficiency loss in switching applications. The gate-to-drain overlap capacitance can be reduced by narrowing the width of the planar gate, i.e., shortening the distance separating the two source regions 112 on either side of the planar gate. However, narrowing the width of the planar gate also narrows the distance d1 between the two body regions 114 on either side of the planar gate. Narrowing the distance d1 can cause the body region boundaries to become too close, resulting in an increased drain resistance due to depletion region pinch-off. Thus, in most cases, a minimum poly gate width is required to avoid pinch-off in the drain drift region of the planar vertical DMOS transistor.